PIC18LF66K80-I/PT【PDF 89/351 页】MCU PIC ECAN 64KB FLASH 64TQFP

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Sheet目录3841

85页 86页 87页 88页 [89页]90页 91页 92页 93页

2010-2012 Microchip Technology Inc.

DS39977F-page 179

PIC18F66K80 FAMILY

RB4/AN9/C2INA/

ECCP1/P1A/CTPLS/

KBI0

RB4

DIG

LATB<4> data output.

PORTB<4> data input; weak pull-up when RBPU bit is cleared.

AN9

ANA

A/D Input Channel 9 and Comparator C2+ input. Default input

configuration on POR; not affected by analog output.

C2INA(1)

ANA

Comparator 2 Input A.

ECCP1(1)

DIG

ECCP1 compare output and ECCP1 PWM output. Takes priority

over port data.

ECCP1 capture input.

P1A(1)

DIG

ECCP1 Enhanced PWM output, Channel A. May be configured for

tri-state during Enhanced PWM shutdown events. Takes priority

over port data.

CTPLS

DIG

CTMU pulse generator output.

KBI0

Interrupt-on-pin change.

RB5/T0CKI/T3CKI/

CCP5/KBI1

RB5

DIG

LATB<5> data output.

PORTB<5> data input; weak pull-up when RBPU bit is cleared.

T0CKI(3)

Timer0 clock input.

T3CKI(4)

Timer3 clock input.

CCP5

DIG

CCP5 compare/PWM output. Takes priority over port data.

CCP5 capture input.

KBI1

Interrupt-on-pin change.

RB6/PGC/TX2/CK2/

KBI2

RB6

DIG

LATB<6> data output.

PORTB<6> data input; weak pull-up when RBPU bit is cleared.

PGC

Serial execution (ICSP) clock input for ICSP and ICD operation.

TX2(1)

DIG

Asynchronous serial data output (EUSARTx module); takes priority

over port data.

CK2(1)

DIG

Synchronous serial clock output (EUSARTx module); user must

configure as an input.

Synchronous serial clock input (EUSARTx module); user must

configure as an input.

KBI2

Interrupt-on-pin change.

RB7/PGD/T3G/RX2/

DT2/KBI3

RB7

DIG

LATB<7> data output.

PORTB<7> data input; weak pull-up when RBPU bit is cleared.

PGD

DIG

Serial execution data output for ICSP and ICD operation.

Serial execution data input for ICSP and ICD operation.

T3G

Timer3 external clock gate input.

RX2(1)

Asynchronous serial receive data input (EUSARTx module).

DT2(1)

DIG

Synchronous serial data output (AUSART module); takes priority

over port data.

Synchronous serial data input (AUSART module); user must

configure as an input.

KBI3

Interrupt-on-pin change.

TABLE 11-3:

PORTB FUNCTIONS (CONTINUED)

Pin Name

Function

TRIS

Setting

I/O

I/O Type

Description

Legend:

O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input;

= Don’t care (TRIS bit does not affect port direction or is overridden for this option)

Note

This pin assignment is only available for 28-pin devices (PIC18F2XK80).

This is the default pin assignment for CANRX and CANTX when the CANMX Configuration bit is set.

This is the default pin assignment for T0CKI when the T0CKMX Configuration bit is set.

This is the default pin assignment for T3CKI for 28, 40 and 44-pin devices. This is the alternate pin assignment for

T3CKI for 64-pin devices when T3CKMX is cleared.

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